References

Goran, P., 2014. A methodology for designing low power sensor node hardware systems. MSc Thesis, Brandenburg University of Technology Cottbus-Senftenberg, Senftenberg, Germany.

Khosrow, G., 2007. Physical Design Essentials. Springer, Berlin, Germany, ISBN:0-387-36642-3,.

Lakshmi, M.S., P. Vaya and S. Venkataramanan, 2011. Power management in SoC using CPF. Proceedings of the 3rd International Conference on Electronics Computer Technology (ICECT) Vol. 2, April 8-10, 2011, IEEE, Kanyakumari, India, ISBN:978-1-4244-8678-6, pp: 325-329.

Liu, S.S.Y., W.T. Lo, C.J. Lee and H.M. Chen, 2013. Agglomerative-based flip-flop merging and relocation for signal wire length and clock tree optimization. ACM. Trans. Des. Autom. Electron. Syst., Vol. 18, 10.1145/2491477.2491484

Melikyan, V., T. Hakhverdyan, S. Manukyan, A. Gevorgyan and D. Babayan, 2016. Low power open RISC processor with power gating, multi-VTH and multi-voltage techniques. Proceedings of the IEEE East-West Design & Test Symposium (EWDTS), October 14-17, 2016, IEEE, Yerevan, Armenia, ISBN:978-1-5090-0694-6, pp: 1-4.

Mutoh, S.I., T. Douseki, Y. Matsuya, T. Aoki and S. Shigematsu et al., 1995. 1-V power supply high-speed digital circuit technology with multi threshold-voltage CMOS. IEEE. J. Solid State Circuits, 30: 847-854.
CrossRef  |  Direct Link  |  

PFI., 2008. A practical guide to low-power design-user experience with CPF. Power Forward Initiative, San Diego, California.

Priya, M.G. and K. Baskaran, 2013. Low power full adder with reduced transistor count. Intl. J. Eng. Trends Technol., 4: 1755-1759.
Direct Link  |  

Santos, C., R. Reis, G. Godoi, M. Barros and F. Duarte, 2012. Multi-bit flip-flop usage impact on physical synthesis. Proceedings of the 25th Symposium on Integrated Circuits and Systems Design (SBCCI), August 30-September 2, 2012, IEEE, Brasilia, Brazil, ISBN:978-1-4673-2606-3, pp: 1-6.

Shyu, Y.T., J.M. Lin, C.P. Huang, C.W. Lin and Y.Z. Lin et al., 2013. Effective and efficient approach for power reduction by using multi-bit flip-flops. IEEE. Trans. Very Large Scale Integr. Syst., 21: 624-635.
CrossRef  |  Direct Link  |  

Wei, L., Z. Chen, K. Roy, M.C. Johnson and Y. Ye et al., 1999. Design and optimization of dual-threshold circuits for low-voltage low-power applications. IEEE. Trans. Very Large Scale Integr. Syst., 7: 16-24.
CrossRef  |  Direct Link  |