References

Adham, S. and B. Nadeau-Dostie, 2004. A BIST algorithm for bit/group write enable faults in SRAMs. Proceedings of the 2004 International Workshop on Memory Technology, Design and Testing, August 10-10, 2004, IEEE, San Jose, California, USA., pp: 98-101.

Harutyunyan, G., A. Hakhumyan, S. Shoukourian, V.A. Vardanian and Y. Zorian, 2011. Symmetry measure for memory test and its application in bist optimization. J. Electron. Test., 27: 753-766.
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Ivaniuk, A.A., 2008. Optimal memory tests coding for programmable BIST architecture. J. Electron. Test., 1: 32-37.
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Ko, Y.C. and S.H. Huang, 2017. 3D IC memory BIST controller allocation for test time minimization under power constraints. Proceedings of the 2017 IEEE 26th International Symposium on Asian Test (ATS), Novomber 27-30, 2017, IEEE, Taipei, Taiwan, ISBN:978-1-5386-3516-2, pp: 260-265.

Miyazaki, M., T. Yoneda and H. Fujiwara, 2006. A memory grouping method for sharing memory BIST logic. Proceedings of the 2006 International Conference on Asia and South Pacific Design Automation, January 24-27, 2006, IEEE, Piscataway, New Jersey, USA., ISBN: 0-7803-9451-8, pp: 671-676.

Tehranipour, M.H., S.M. Fakhraie, Z. Navabi and M.R. Movahedin, 2004. A low-cost at-speed bist architecture for embedded processor and sram cores. J. Electron. Test., 20: 155-168.
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Yeh, C.H., C.H. Cheng and S.H. Huang, 2016. Grouping and placement of memory BIST controllers for test application time minimization. Proceedings of the 2016 5th International Symposium on Next-Generation Electronics (ISNE), May 4-6, 2016, IEEE, Hsinchu, Taiwan, pp: 1-2.

Zorian, Y. and H. Bederr, 1997. An effective multi-chip BIST scheme. J. Electron. Test., 10: 87-95.
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