Journal of Engineering and Applied Sciences

Year: 2020
Volume: 15
Issue: 2
Page No. 501 - 507

Performance Analysis of 6-Transistor Full Adder Circuit using PTM 32 nm Technology LP-MOSFETs and DG-FinFETs

Authors : S.M.Ishraqul Huq

References

Chandra, K., R. Kumar, S. Uniyal and V. Ramola, 2015. A new design 6T full adder circuit using novel 2T XNOR gates. IOSR. J. VLSI. Signal Process., 5: 63-68.

Chin, H.C., C.S. Lim and M.L.P. Tan, 2015. Design and performance analysis of 1-bit FinFET full adder cells for subthreshold region at 16 nm process technology. J. Nanomaterials, Vol. 16,

Dwivedi, S. and N.R. Prakash, 2016. Design of an energy efficient half adder, code convertor and full adder in 45nm CMOS technology. Int. J. Sci. Eng. Res., 7: 473-478.
Direct Link  |  

Kumar, M., S.K. Arya and S. Pandey, 2012. Low power CMOS full adder design with 12 transistors. Int. J. Inf. Technol. Convergence Serv., 2: 11-21.
Direct Link  |  

Liu, T.J.K., 2012. FinFET history, fundamentals and future. Proceedings of the International Symposium on VLSI Technology Short Course, June 11, 2012, University of California, Berkeley, USA., pp: 1-55.

Morgenshtein, A., A. Fish and A. Wagner, 2001. Gate-Diffusion Input (GDI)-A novel power efficient method for digital circuits: A design methodology. Proceedings of the 14th Annual IEEE International ASIC/SOC Conference (IEEE Cat. No. 01TH8558), September 12-15, 2001, IEEE, Arlington, Virginia, USA., pp: 39-43.

Navi, K., O. Kavehei, M. Rouholamini, A. Sahafi, S. Mehrabi and N. Dadkhahi, 2008. Low-power and high-performance 1-Bit CMOS full-adder cell. J. Comput., 3: 48-54.
CrossRef  |  Direct Link  |  

Priyanka, P. and K.S.V. Patel, 2015. Design and implementation of high-performance logic arithmetic full adder circuit based on FinFET 16nm technology-shorted gate mode. Int. J. Sci. Res., 4: 490-494.
Direct Link  |  

Reddy, K.G., 2013. Low power-area designs of 1bit full adder in cadence Virtuoso platform. Int. J. VLSI Design Commun. Syst., 4: 55-64.
CrossRef  |  Direct Link  |  

Singh, N., M. Kaur, A. Singh and P. Jain, 2014. An efficient full adder design using different logic styles. Int. J. Comput. Appl., 98: 38-41.
Direct Link  |  

Zimmermann, R. and W. Fichtner, 1997. Low-power logic styles: CMOS versus pass-transistor logic. IEEE J. Solid-State Circ., 32: 1079-1090.
CrossRef  |  Direct Link  |  

Design and power by Medwell Web Development Team. © Medwell Publishing 2024 All Rights Reserved