Authors : P. Arun Kumar, P. Pandian and Raja Paul Perinbham
Abstract: Researchers present a Fault Tolerant Hardware Routing Model using reusability technique for the Network on Chips (NOC) during faulty conditions to enable the router to transmit the packets effectively without any loss. The network has been designed for 3x3 and 4x4. The faults are mainly injected due to transients in the real world which affects the routing path and they are modeled as digital faults. The reliability of the design has been found out to be 100% for bidirectional design of NOC routers at a frequency of 500 MHz.
P. Arun Kumar, P. Pandian and Raja Paul Perinbham, 2014. Reusable Network on Chip Design. International Journal of Soft Computing, 9: 235-239.