Asian Journal of Information Technology

Year: 2016
Volume: 15
Issue: 2
Page No. 263 - 276

Multi-Core Lifting DWT Processing Engines for Image Processing

Authors : M. Nagabushanam and P. Kumar

References

Andra, K., C. Chakrabarti and T. Acharya, 2002. A VLSI architecture for lifting-based forward and inverse wavelet transform. IEEE Trans. Signal Process., 50: 966-977.
CrossRef  |  

Chiang, J.S., C.H. Hsia, H.J. Chen and T.J. Lo, 2005. VLSI architecture of low memory and high speed 2D lifting-based discrete wavelet transform for JPEG2000 applications. Proceedings of the IEEE International Symposium on Circuits and Systems ISCAS 2005, May 23-26, 2005, IEEE, USA., pp: 4554-4557.

Dai, Q., X. Chen and C. Lin, 2004. A novel VLSI architecture for multidimensional discrete wavelet transform. Circuits Syst. Video Technol. IEEE. Trans., 14: 1105-1110.
CrossRef  |  Direct Link  |  

Das, A., A. Hazra and S. Banerjee, 2010. An efficient architecture for 3-D discrete wavelet transform. IEEE Trans. Circuits Syst. Video Technol., 20: 286-296.
Direct Link  |  

Das, B. and S. Banerjee, 2005. Data-folded architecture for running 3D DWT using 4-tap daubechies filters. Circuits, Devices Syst. IEE. Proc., 152: 17-24.
CrossRef  |  Direct Link  |  

Hegde, G. and P. Vaya, 2013. A parallel 3-D discrete wavelet transform architecture using pipelined lifting scheme approach for video coding. Int. J. Electr., 100: 1429-1440.
CrossRef  |  Direct Link  |  

Hu, Y. and C.C. Jong, 2013. A memory-efficient high-throughput architecture for lifting-based multi-level 2-D DWT. Signal Proc. IEEE. Trans., 61: 4975-4987.
CrossRef  |  Direct Link  |  

Mohanty, B.K. and P.K. Meher, 2013. Memory-efficient high-speed convolution-based generic structure for multilevel 2-D DWT. IEEE. Trans. Circ. Syst. Video Technol., 23: 353-363.
CrossRef  |  Direct Link  |  

Mottaghi-Dastjerdi, M., A. Afzali-Kusha and M. Pedram, 2009. BZ-FAD: A low-power low-area multiplier based on shift-and-add architecture. IEEE. Trans. Very Large Scale Integr. Syst., 17: 302-306.
CrossRef  |  Direct Link  |  

Nagabushanam, M. and S. Ramachandran, 2012. Fast implementation of lifting based 1D/2D/3D DWT-IDWT architecture for image compression. Int. J. Comput. Applic., 51: 35-41.
CrossRef  |  Direct Link  |  

Parhi, K.K. and T. Nishitani, 1993. VLSI architectures for discrete wavelet transforms. Very Large Scale Integr. Syst. IEEE. Trans., 1: 191-202.
CrossRef  |  Direct Link  |  

Sung, T.Y., H.C. Hsin, Y.S. Shieh and C.W. Yu, 2006. Low-power multiplierless 2-D DWT and IDWT architectures using 4-tap daubechies filters. Proceedings of the Seventh International Conference on Parallel and Distributed Computing, Applications and Technologies, 2006 PDCAT'06, December 4-7, 2006, IEEE, Taipei, Taiwan, pp: 185-190.

Taghavi, Z. and S. Kasaei, 2003. A memory efficient algorithm for multi-dimensional wavelet transform based on lifting. Proceedings of the 2003 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP'03), April 6-10, 2003, IEEE, USA., pp: 401-404.

Xu, J., Z. Xiong, S. Li and Y.Q. Zhang, 2002. Memory-constrained 3D wavelet transform for video coding without boundary effects. Circuits Syst. Video Technol. IEEE. Trans., 12: 812-818.
CrossRef  |  Direct Link  |  

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