References

Breuer, M.A., 1977. A class of min-cut placement algorithms. Proceedings of the 14th International Conference on Design Automation (DAC'77), January 1, 1977, IEEE Press, Piscataway, New Jersey, USA., pp: 284-290.

Cousin, J.G., O. Sentieys and D. Chillet, 2000. Multi-algorithm ASIP synthesis and power estimation for DSP applications. Proceedings of the 2000 IEEE International Symposium on Circuits and Systems Emerging Technologies for the 21st Century (IEEE Cat No. 00CH36353) Vol. 2, May 28-31, 2000, IEEE, Geneva, Switzerland, ISBN:0-7803-5482-6, pp: 621-624.

Dhanwada, N., R. Davis and J. Frenkil, 2014. Towards a standard flow for system level power modeling. Proceedings of the 2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), November 2-6, 2014, IEEE, San Jose, California, USA., ISBN:978-1-4799-6278-5, pp: 73-73.

Dunlop, A.E. and B.W. Kernighan, 1985. A procedure for placement of standard-cell VLSI circuits. IEEE. Trans. Comput. Aided Des., 4: 92-98.
CrossRef  |  Direct Link  |  

Keating, M., D. Flynn, R. Aitken, A. Gibbons and K. Shi, 2011. Low Power Methodology Manual: For System-on-Chip Design. 2nd Edn., Springer, New York, USA., Pages: 300.

Khalifa, K. and K. Salah, 2016. An RTL power optimization technique based on system Verilog assertions. Proceedings of the IEEE 7th Annual International Conference on Ubiquitous Computing, Electronics & Mobile Communication (UEMCON), October 20-22, 2016, IEEE, New York, USA., ISBN:978-1-5090-1497-2, pp: 1-4.

Kleinhans, J.M., G. Sigl, F.M. Johannes and K.J. Antreich, 1991. GORDIAN: VLSI placement by quadratic programming and slicing optimization. IEEE. Trans. Comput. Aided Des. Integr. Circuits Sys., 10: 356-365.
CrossRef  |  Direct Link  |  

Macii, E., 1997. High-Level Synthesis for Low Power. In: Low Power Design in Deep Submicron Electronics, Nebel, W. and J. Mermet (Eds.). Springer, Berlin, Germany, ISBN:978-0-7923-8103-7, Boston, Massachusetts, USA., pp: 381-393.

Rabaey, J.M., A.P. Chandrakasan and B. Nikolic, 2003. Digital Integrated Circuits: A Design Perspective. 2nd Edn., Pearson, New York, USA., Pages: 761.

Reyes, E.N. and C. Steidley, 1998. Optimization using simulated annealing. Proceedings of the International Conference on Northcon/98 (Cat. No.98CH36264), October 21-23, 1998, IEEE, Seattle, WA, USA., ISBN:0-7803-5075-8, pp: 120-126.

Sun, W.J. and C. Sechen, 1995. Efficient and effective placement for very large circuits. IEEE. Trans. Comput. Aided Des. Integr. Circuits Sys., 14: 349-359.
CrossRef  |  Direct Link  |  

Wang, Q. and S. Roy, 2003. RTL power optimization with gate-level accuracy. Proceedings of the International Conference on Computer Aided Design ICCAD-2003 (IEEE Cat. No.03CH37486), November 9-13, 2003, IEEE, San Jose, California, USA., ISBN:1-58113-762-1, pp: 39-45.