Authors : S. Lakshmi Narayanan, Reeba Korah and A. Swarnalatha
Abstract: IC technology demands high performance, low power consuming, miniature sized devices. Minimizing the device size drastically increases the power consumption and hence the need for innovative techniques to reduce the power consumption are in the bloom. The approach accorded here is the combined implementation of leakage controlled transistors in the path between power supply and ground and stacking of transistors in the pull down network. The above approach is implemented in Domino logic circuits which are often claimed as leaky circuits. Results show reduction in leakage current, total power consumption with an admissible increase in transistor count and overall delay.
S. Lakshmi Narayanan, Reeba Korah and A. Swarnalatha, 2016. Leakage Current Minimization in Footerless Domino Logic Circuits Using Stalk Technique. Asian Journal of Information Technology, 15: 2578-2583.