Authors : Nasseer M. Basheer and Enas Ali Ahmed
Abstract: The implementation of Advanced Encryption Standard (AES) algorithm for encryption and decryption using a Finite-State Machine (FSM) is proposed in this study. The programming language used is the VHDL (Very High speed integrated circuit hardware Description Language). Xilinx_ISE_10.1 Software is used to simulate the synthesizable VHDL code. The obtained results are being synthesized and simulated through using Xilinx ISE 10.1 Software. A Finite State Machine (FSM) approach with block and key size of 128 bits is used in this design. Other previous reported works are also mentioned. A throughput of 1.349 Gbps for encryption process and 1.012 Gbps for decryption process are resulted by the implementation of the algorithm using (FSM) approach. Depending on the synthesis report the number of slices is 2156 (46% of total resources) for encryption and 2354 (50% of total resoures) for decryption. VHDL test bench waveform of Xilinx ISE10.1 is used to test the work of the implemented algorithm. The hardware kit used is the Spartan3e XC3s500e FPGA.
Nasseer M. Basheer and Enas Ali Ahmed, 2018. A VHDL Implementation Encryption and Decryption of the Advanced Encryption Standard (AES) Algorithm. Journal of Engineering and Applied Sciences, 13: 10564-10570.