References

Dabholkar, V., S. Chakravarty, I. Pomeranz and S. Reddy, 1988. Techniques for minimizing power dissipation in scan and combinational circuits during test application. IEEE. Trans. Comput. Aided Des. Integr. Circuits Syst., 17: 1325-1333.
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Kajihara, S., K. Ishida and K. Miyase, 2002. Test vector modification for power reduction during scan testing. Proceedings of the Symposium on VLSI Test Symposium (VTS 2002), May 2, 2002, IEEE, Monterey, California, ISBN: 0-7695-1570-3, pp: 160-165.

Lee, K.J., T.C. Haung and J.J. Chen, 2000. Peak-power reduction for multiple-scan circuits during test application. Proceedings of the 9th Asian Symposium on Test Symposium, December 4-6, 2000, IEEE, Taipei, Taiwan, ISBN: 0-7695-0887-1, pp: 453-458.

Sankaralingam, R., R.R. Oruganti and N.A. Touba, 2000. Static compaction techniques to control scan vector power dissipation. Proceedings of the 18th IEEE VLSI Test Symposium, April 30, 2000, IEEE, Montreal, Quebec, ISBN: 0-7695-0613-5, pp: 35-40.

Whetsel, L., 2000. Adapting scan architectures for low power operation. Proceedings of the International Conference on Test Conference, October 3-5, 2000, IEEE, Atlantic, New Jersey, ISBN: 0-7803-6546-1, pp: 863-872.