References

Baliga, B.J., 2010. Fundamentals of Power Semiconductor Devices. Springer Science & Business Media, Berlin, Germany,.

Haynie, S., A. Gabrys, T. Kwon, P. Allard and J. Strout et al., 2010. Power LDMOS with novel STI profile for improved Rsp, BVdss and reliability. Proceedings of the 2010 22nd International Symposium on Power Semiconductor Devices & IC's (ISPSD), June 6-10, 2010, IEEE, New York, USA., ISBN:978-1-4244-7718-0, pp: 241-244.

Kim, M.H., J.J. Kim, Y.S. Choi, C.K. Jeon and S.L. Kim et al., 2003. A low on resistance 700V charge balanced LDMOS with intersected WELL structure. Proceedings of the 2003 IEEE 15th International Symposium on Power Semiconductor Devices and ICs, ISPSD'03, April 14-17, 2003, IEEE, New York, USA., ISBN:0-7803-7876-8, pp: 220-223.

Kim, S.L., H.Y. Yang, Y.I. Choi, S.K. Chung and M.K. Han, 1999. A low on-resistance SOI LDMOS with an elevated internal ring. Physica Scr., 1999: 303-306.
Direct Link  |  

Kumar, M.J. and A. Bansal, 2012. Improving the breakdown voltage, ON-resistance and gate-charge of InGaAs LDMOS power transistors. Semicond. Sci. Technol., Vol. 27,

Kwon, H., C.U. Yoo, M.S. Kim and Y. Yang, 2009. A study on efficiency improvement of Doherty amplifier using LDMOS FET for WiMax networks. Proceedings of the 11th International Conference on Advanced Communication Technology, ICACT 2009, Vol. 2, February 15-18, 2009, IEEE, New York, USA., ISBN:978-89-5519-138-7, pp: 1406-1409.

Kwon, T.H., Y.S. Jeoung, S.K. Lee, Y.C. Choi and C.J. Kim et al., 2002. Newly designed isolated RESURF LDMOS transistor for 60 V BCD process provides 20 V vertical NPN transistor. Proceedings of the 60th Conference on Device Research, DRC 2002, June 24-26, 2002, IEEE, New York, USA., ISBN:0-7803-7317-0, pp: 67-68.

Minasian, R.A., 1983. Power MOSFET dynamic large-signal model. IEE. Proc. I Solid State Electron. Devices, 130: 73-79.
Direct Link  |  

Nemati, H.M., C. Fager, M. Thorsell and H. Zirath, 2009. High-efficiency LDMOS power-amplifier design at 1 GHz using an optimized transistor model. IEEE. Trans. Microwave Theor. Tech., 57: 1647-1654.
CrossRef  |  Direct Link  |  

Ramarao, B.V., J.K. Mishra, M. Pande, P. Singh and G. Kumar et at., 2013. Comparison Study of LDMOS and VDMOS Technologies for RF Power Amplifiers. In: AIP Conference Proceedings, Chauhan, A.K., C. Murli and S.C. Gadkari (Eds.). AIP Publishing, Melville, New York, pp: 492-493.

Sithanandam, R. and M.J. Kumar, 2009. Linearity and speed optimization in SOI LDMOS using gate engineering. Semicond. Sci. Technol., Vol. 25,

Son, M.H., S. Bae, H. Park and H.M. Kwon, 2016. The effect of void on characteristics of LDMOS power amplifier. Microwave Opt. Technol. Lett., 58: 691-694.
CrossRef  |  Direct Link  |  

Wu, L., W. Zhang, Q. Shi, P. Cai and H. He, 2014. Trench SOI LDMOS with vertical field plate. Electron. Lett., 50: 1982-1984.
Direct Link  |  

Zeghbroeck, B.V., 2007. Principles of semiconductor devices. http://www.chtm.unm.edu/sigmon/EE576/EE576.html.

Zhou, M.J. and A.V. Calster, 1994. A breakdown voltage model for implanted RESURF p-LDMOS device on n+ buried layer. Solid State Electron., 37: 1383-1385.
Direct Link  |