Journal of Engineering and Applied Sciences

Year: 2018
Volume: 13
Issue: 16
Page No. 6855 - 6859

A New Physical Design Approach for Setup Timing Optimization in 7 nm Global Routed Designs

Authors : Mohamed Chentouf, Lekbir Cherif and Zine El Abidine Alaoui Ismaili

References

Alaghi, A., W.T.J. Chan, J.P. Hayes, A.B. Kahng and J. Li, 2017. Trading accuracy for energy in stochastic circuit design. ACM. J. Emerging Technol. Comput. Syst., 13: 1-30.
CrossRef  |  Direct Link  |  

Alpert, C. and A. Devgan, 1997. Wire segmenting for improved buffer insertion. Proceedings of the 34th Annual Conference on Design Automation, June 09-13, 1997, ACM, Anaheim, California, USA., ISBN:0-89791-920-3, pp: 588-593.

Bhasker, J. and R. Chadha, 2009. Static Timing Analysis for Nanometer Designs: A Practical Approach. Springer, New York, USA., ISBN:978-0-387-93819-6, Pages: 572.

Bhattacharya, S., D. Das and H. Rahaman, 2016. Delay minimization of multilayer graphene nanoribbon based interconnect using wire sizing method. Proceedings of the 2016 International Conference on Microelectronics, Computing and Communications (MicroCom’16), January 23-25, 2016, IEEE, Durgapur, India, ISBN:978-1-4673-6622-9, pp: 1-6.

Chen, S. and X. Liu, 2007. A low-latency and low-power hybrid insertion methodology for global interconnects in VDSM designs. Proceedings of the 1st International Symposium on Networks-on-Chip (NOCS’07), May 7-9, 2007, IEEE, Princeton, New Jersey, USA., pp: 75-82.

Chen, X., X. Huang, Y. Xiang, D. Zhang and R. Ranjan et al., 2017. A CPS framework based perturbation constrained buffer planning approach in VLSI design. J. Parallel Distrib. Comput., 103: 3-10.
CrossRef  |  Direct Link  |  

Karimi, G. and A. Ahmadi, 2014. Buffer insertion for delay minimization using an improved PSO algorithm. Appl. Math. Inf. Sci., 8: 2277-2285.
Direct Link  |  

Liu, L., Y. Zhou and S. Hu, 2014. Buffering single-walled carbon nanotubes bundle interconnects for timing optimization. Proceedings of the 2014 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), July 9-11, 2014, IEEE, Tampa, Florida, ISBN:978-1-4799-3765-3, pp: 362-367.

Murgai, R., 2015. Technology-dependent logic optimization. Proc. IEEE., 103: 2004-2020.
CrossRef  |  Direct Link  |  

Rabaey, J.M., A.P. Chandrakasan and B. Nikolic, 2003. Digital Integrated Circuits: A Design Perspective. 2nd Edn., Pearson, New York, USA., Pages: 761.

Sarfati, E., B. Frankel, Y. Birk and S. Wimer, 2017. Optimal VLSI delay tuning by space tapering with clock-tree application. IEEE. Trans. Circuits Syst. I Regul. Pap., 64: 2160-2170.
CrossRef  |  Direct Link  |  

Zhang, H., M.D. Wong, K.Y. Chao and L. Deng, 2012. A practical low-power nonregular interconnect design with manufacturing for design approach. IEEE. J. Emerging Sel. Top. Circuits Syst., 2: 322-332.
CrossRef  |  Direct Link  |  

Design and power by Medwell Web Development Team. © Medwell Publishing 2024 All Rights Reserved