Journal of Engineering and Applied Sciences
Year:
2019
Volume:
14
Issue:
4
Page No.
1070 - 1077
References
Baugh, C.R. and B.A. Wooley, 1973. A two's complement parallel array multiplication algorithm. IEEE. Trans. Comput., 100: 1045-1047.
Direct Link | Bougas, P., P. Kalivas, A. Tsirikos and K.Z. Pekmestzi, 2015. Pipelined array-based FIR filter folding. IEEE. Trans. Circuits Syst. I Regul. Pap., 52: 108-118.
CrossRef | Direct Link | Brent, R.P., 1982. A regular layout for parallel adders. IEEE Trans. Comput., c-31: 260-264.
Direct Link | Mudassir, R. and Z. Abid, 2005. New parallel multipliers based on low power adders. Proceedings of the Canadian Conference on Electrical and Computer Engineering, May 1-4, 2005, Canada, pp: 694-697.
Parhi, K.K., C.Y. Wang and A.P. Brown, 1992. Synthesis of control circuits in folded pipelined DSP architectures. IEEE. J. Solid State Circuits, 27: 29-343.
Direct Link | Wang, Y., Y. Jiang and E. Sha, 2001. On area-efficient low power array multipliers. Proceedings of the 8th IEEE International Conference on Electronics, Circuits and Systems (ICECS’01) Vol. 3, September 2-5, 2001, IEEE, Malta, Europe, pp: 1429-1432.
Yu, Z., M.L. Yu, K. Azadet and A.N. Willson, 2002. A low power adaptive filter using dynamic reduced 2’s-complement representation. Proceedings of the 2002 IEEE Conference on Custom Integrated Circuits, May 15, 2002, IEEE, Orlando, Florida, pp: 141-144.