Abstract: A simple analytical expression for the 2D potential distribution in the Si channel n-MOS has been derived in the weak inversion regime. The analytical model includes the effect of short channel length, the influence of source to drain field on the substrate depletion depth through Voltage Doping Transformation (VDT), high-k dielectrics, interface trap charge density (Dit), gate work function and other device parameters. The analytical solution of the surface potential has been verified by the numerical solution of 2D Poisson’s equation for two different values, the drain to source voltage V_DS with close agreement. Based on this model, the expression for threshold voltage V_TH, drain induced barrier lowering DIBL and the subthreshold slope S have been deduced. This model predictions show satisfactory agreement with the 2D numerical simulation results obtained by using MEDICI and also with reported experimental data. Further applying the model, threshold voltage and subthreshold slope have been comprehensively investigated.

INTRODUCTON

Recently, Silicon (Si) has emerged as a promising high mobility channel material, alternative to germanium for future high performance n-MOS devices (Yamamoto et al., 2007; Nicholas et al., 2007; Zimmerman et al., 2006). The bulk hole mobility of Silicon is the highest of all group 4 and 3-5 semiconductor materials. There have been several reports of Si channel n-MOS with a variety of surface passivation schemes (Shasng et al., 2002; Chui et al., 2002). Some research groups performed TCAD simulations in order to forecast, the enhanced performance of Si channel n-MOS with different kinds of metal gate stacks (Mandal et al., 2005; Skotnicki et al., 1988). However, the analytical model for computing key performance parameters of the device such as threshold voltage, drain induced barrier lowering and the subthreshold slope based on the 2D surface potential approach is hardly available in the literature (Pershenkov et al., 1999).

In this study, we have shown an analytical model for the calculation of threshold voltage, drain induced barrier lowering and subthreshold slope of Si channel n-MOS devices with gate stacks (Bai et al., 2003; Taurus Medici, 2009). This model formulation entails the effect of short channel, the impact of source to drain electric field on the substrate depletion width, the interface trap density, high metal gate stacks and other material and device parameters. Based on the model, we have comprehensively investigated threshold voltage and subthreshold slope for a wide range of channel length L, Equivalent Oxide Thickness (EOT) and interface trap density.

MODELING AND SIMULATION

Formulation: A sandwich of thin oxide, silicon nitride and another thin oxide is prepared on the surface of a clean wafer. The first oxide acts as a buffer to relieve mechanical stress due to unequal thermal expansion of the substrate and nitride. The nitride also acts as a shield to prevent oxidation of the active region during field oxide growth. A layer of photo resist is deposited on the entire surface. Using a diffusion layer, the thin oxide and nitride are etched out. The open area is called as the field oxide region. A p⁺ region is created by ion implantation which acts as a channel stop. A thick oxide about 1 μm is grown on top of the implanted region which together with channel stops serves neighboring active region. After this, the remaining oxide and nitride are removed. The active area will now be used for source, drain and channel regions for all transistors plus any diffusion wire needed for interconnect (Fig. 1). Electric flux at the gate-oxide and silicon channel interface is continuous, i.e.:

(1)

Where, φ_fb is the flat band voltage and defined as:

Fig. 1:	a) A layer of photo resist deposited on the entire surface; b) thick oxide layer; c) oxide and nitrate removal and d) top view of the inverter circuit

φ_ms is the work function of the gate material with respect to silicon and Q_it is the interface trapped charge density per unit area given by:

D_it being the interface trap density:

is the Fermi potential in the bulk silicon:

is the capacitance across the gate oxide, V_t is the thermal voltage and n_i is the intrinsic carrier concentration of Si. The electric field vanishes at the depletion depth, i.e:

(2)

Using Eq. 1 and 2, the coefficients C₁(x) and C₂(x) can be deduced as:

(3)

and;

(4)

Substituting these values in Eq. 1, we obtain:

(5)

Where:

(6)

The solution can be written as:

(7)

Where:

By using boundary conditions, we obtain:

and:

(8)

In order to calculate the threshold voltage, one must know the maximum value of surface potential which is found from by setting:

(9)

The maximum surface potential is evaluated as:

(10)

The threshold voltage is an important electrical parameter which determines the electrical behavior of the MOS device. The threshold voltage V_TH is the value of the gate voltage at which:

(11)

Substituting the value of V_TH can be obtained as:

(12)

Where:

Voltage-Doping Transformation (VDT): The influence of source-drain electric field on the potential barrier height has been identified as one of the important components of Short Channel Effects (SCEs). This effect can be taken into account by simply modifying the channel doping concentration, employing the voltage-doping transformation following: The modified channel doping concentration N^*(x) can be deduced from the 2-D Poisson equation and is expressed as:

(13)

Where:

The drain induced barrier lowering DIBL can be computed as:

(14)

Where, V_TH1 and V_TH2 are the value of threshold voltages at V_DS1 and V_DS2, respectively. The high drain to source voltage, V_DS1 is set at -1 V and the low drain to source voltage V_DS2 is connected to -50 mV.

The subthreshold slope S is of great concern in controlling the turn-off characteristic of MOS. The smaller the slope, the lower the off state power of the device. The subthreshold slope S can be expressed as:

(15)

Where:

RESULTS AND DISCUSSION

In order to verify the proposed analytical model, we have compared the theoretical results for the threshold voltage, Drain Induced Barrier Lowering (DIBL) and the subthreshold slope with the experimental data, reported for various channel lengths of silicon channel n-MOS. Furthermore, the 2-D device simulator MEDICI was employed to simulate the transfer characteristic of the Si channel n-MOS devices for a wide range of geometrical and material parameters. The characteristics have been utilized to extract the simulation value of threshold Voltage V_TH, drain induced barrier lowering DIBL and the subthreshold slope S. The simulation value of threshold voltage corresponds to the gate voltage at which volume density of inversion charge becomes equal to the channel doping concentration consistent with the model formulation. For low and high values of drain-source Voltage (V_DS). The maximum value of the surface potential occurs at the middle of the channel length for a low value of:

while the maximum value of surface potential shifts towards the source end for higher value of:

A large value of the maximum surface potential corresponds to a higher value of the threshold voltage of the device (Fig. 2). Figure 3 shows the analytical, simulation simulation and experimental results of simulation and experimental results of voltage for different values of channel length in the range 125 nm-10 μm for Si channel n-MOS devices.

Fig. 2:	Variation of surface potential with the normalized distance along the channel with VDS = -50 mV and VDS = -1 V

Fig. 3:	Comparison of analytical, simulation and experimental results for different values of channel length with VDS = -50 mV (Zimmerman et al., 2006)

Fig. 4:	Plot of DIBL against channel length with VDS = -50 mV (Zimmerman et al., 2006)

Some important features are as follows: channel doping concentration is 5x10¹⁶ cm^-3 and a gate stack capped by a 4 nm ALD HfO₂ gate dielectric followed by 10 nm TaN and 80 nm TiN PVD depositions. It is evident that the theoretical predictions for the threshold voltage of Si channel n-MOS devices track satisfactorily with the corresponding simulation value and also with the reported experimental data. We have also plotted the variation of DIBL for Si based n-MOS devices against the channel length (Fig. 4).

Fig. 5:	Dependence of threshold voltage with channel length for different equivalent oxide thickness

Table 1:	Comparison of experimental data and analytical results for subthreshold Slope (S) of Si channel n-MOS devices

One can easily observe from the Fig. 4 that the analytical results for DIBL match well with the reported experimental results. Additionally, the results for the subthreshold slope for three different channel lengths have been shown in Table 1.

Once again, an excellent match between the predictions and reported experimental data is found. Clearly since, the predictions based on the analytical model for threshold voltage V_TH, drain induced barrier, lowering DIBL and subthreshold slope S, match satisfactorily with the simulation results obtained, using MEDICI and also with reported experimental data for various different devices, the validity of the model is clearly ensured. The variation of V_TH with the channel length of the device is shown in Fig. 5 for different values of Equivalent Oxide Thickness (EOT). As EOT increases, V_TH rises and the rate of rise is considerable particularly for channel lengths below 300 nm.

Figure 6 shows the dependence of V_TH against EOT with channel length as a parameter. The sensitivity of V_TH with EOT in particular for EOT <6 nm is considerable and as EOT >6 nm, V_TH increases slowly with EOT. Another notable feature of the plot is that the variation of V_TH with EOT for a shorter channel device is more pronounced than one with a larger channel length. Figure 7 shows the variation of S with both channel length and interface trap density. The dependence of S on L is nonlinear while on D_it is linear.

Fig. 6:	Threshold voltage vs. effective oxide thickness for three different channel length

Fig. 7:	Plot of sub-threshold slope with channel length and Dit for VDS = -50 mV

The sub-threshold slope increases significantly with decreasing channel length particularly for L<250 nm. This feature indicates the early initiation of the short channel effects in comparison with the germanium devices.

CONCLUSION

The influence of various material and device parameters like channel length, equivalent oxide thickness, interface trap density, etc. on the device performance metrics such as threshold voltage, drain induced barrier, lowering and sub-threshold slope of Si channel n-MOS has been intensively investigated by developing an analytical model for the same. Based on the model, the prediction results show satisfactory concordance with the numerical simulation results and also with reported experimental data. Most importantly, the results point out that as the channel length reduces <0.25 μm, the threshold voltage rises considerably indicating the beginning of the short channel effect unlike Si n-MOS. Also both the DIBL and S deteriorate for channel lengths <250 nm.

Further threshold voltage reduces linearly <6 nm of EOT and its rate of rise with EOT is less than linear for EOT >6 nm for channel length in the range 150-250 nm. The model accurately predicts different performance metrics over a large range of material and device parameters and can be effectively employed to design and characterize high performance Si channel n-MOS with the desired performance.