References

Agarwal, A., 1991. Limits on interconnection network performance. IEEE. Trans. Parallel Distrib. Syst., 2: 398-412.
CrossRef  |  Direct Link  |  

Andreasson, D. and S. Kumar, 2005. Slack-time aware routing in NoC systems. Proceedings of the 2005 IEEE International Symposium on Circuits and Systems (ISCAS’05), May 23-26, 2005, IEEE, Kobe, Japan, ISBN:0-7803-8834-8, pp: 2353-2356.

Anjan, K.V. and T.M. Pinkston, 1995. DISHA: A deadlock recovery scheme for fully adaptive routing. Proceedings of the 9th International Symposium on Parallel Processing, April 25-28, 1995, IEEE, Santa Barbara, California, ISBN:0-8186-7074-6, pp: 537-543.

Arns, R.G., 1998. The other transistor: Early history of the metal-oxide semiconductor field-effect transistor. Eng. Sci. Educ. J., 7: 233-240.
CrossRef  |  Direct Link  |  

Ascia, G., V. Catania and M. Palesi, 2004. Multi-objective mapping for mesh-based NoC architectures. Proceedings of the 2nd IEEE-ACM-IFIP International Conference on Hardware-Software Codesign and System Synthesis, September 08-10, 2004, ACM, Stockholm, Sweden, ISBN:1-58113-937-3, pp: 182-187.

Ascia, G., V. Catania, M. Palesi and D. Patti, 2006. Neighbors-on-path: A new selection strategy for on-chip networks. Proceedings of the 2006 IEEE-ACM-IFIP Workshop on Embedded Systems for Real Time Multimedia, October 26-27, 2006, ACM, Washington, DC, USA., ISBN:0-7803-9783-5, pp: 79-84.

Benini, L. and D. Bertozzi, 2005. Network-on-chip architectures and design methods. IEE. Proc. Comput. Digital Tech., 152: 261-272.
CrossRef  |  Direct Link  |  

Bertozzi, D., A. Jalabert, S. Murali, R. Tamhankar, S. Stergiou, L. Benini and G. De Micheli, 2005. NoC synthesis flow for customized domain specific multiprocessor systems-on-chip. IEEE Trans. Parallel Distrib. Syst., 16: 113-129.
CrossRef  |  

Collins, L., 2003. Chip makers hit heat barrier. IEE. Rev., 49: 22-23.
Direct Link  |  

Dally, W.J. and C.L. Seitz, 1987. Deadlock-free message routing in multiprocessor interconnection networks. IEEE Trans. Comput., 36: 547-553.
Direct Link  |  

Dally, W.J. and H. Aoki, 1993. Deadlock-free adaptive routing in multi-computer networks using virtual channels. IEEE. Trans. Parallel Distrib. Syst., 4: 466-475.
CrossRef  |  Direct Link  |  

Flich, J., A. Mejia, P.L Opez and J. Duato, 2007. Region-based routing: An efficient routing mechanism to tackle unreliable hardware in network on chips. Proceedings of the 1st International Symposium on Networks-on-Chip (NOCS'07), May 9, 2007, IEEE Computer Society, Washington, DC., USA., ISBN:0-7695-2773-6, pp: 1-12.

Frazzetta, D., G. Dimartino, M. Palesi, S. Kumar and V. Catania, 2008. Efficient application specific routing algorithms for NoC systems utilizing partially faulty links. Proceedings of the 11th Euro-micro Conference on Digital System Design Architectures Methods and Tools (DSD'08), September 3-5, 2008, IEEE, Parma, Italy, ISBN:978-0-7695-3277-6, pp: 18-25.

Kim, D., M. Kim and G.E. Sobelman, 2004. CDMA-based network-on-chip architecture. Proceedings of the 2004 IEEE Asia-Pacific Conference on Circuits and Systems Vol. 1, December 6-9, 2004, IEEE, Tainan, Taiwan, ISBN:0-7803-8660-4, pp: 137-140.

Su, C.C. and K.G. Shin, 1996. Adaptive fault-tolerant deadlock-free routing in meshes and Hypercubes. IEEE. Trans. Comput., 45: 666-683.
CrossRef  |  Direct Link  |